1. Field of the Invention
The present invention generally relates to methods for laying out integrated circuits.
2. State of the Art
It is well known to use computerized systems for laying out integrated circuits such as application-specific integrated circuits that include a number of functional blocks or "cells." A standard cell within an application-specific integrated circuit may comprise, for example, one or more random access memories (RAMs), read-only memories (ROMs), or arithmetic logic units. During the design of integrated circuits, it is usually necessary to determine the signal delays. Although signal delays can be determined by testing prototype of integrated circuits, prototypes are usually expensive. Accordingly, it is desirable to develop techniques for calculating signal delays prior to laying out integrated circuits.
In practice, however, it is difficult to calculate signal delays in integrated circuits. In part, the difficulties arise because the computational techniques, to be of practical and convenient, must be capable of computing all interconnect delays in integrated circuits having, for example, one-hundred thousand transistors by using a desk-top work station over a time period less than about one hour.
In integrated circuits, signal delays can arise from various sources, including the resistance and capacitance of wires that connect elements within the circuits. Also, delays through gates in integrated circuits depend upon the loads driven by the gates drive and upon the quantity of interconnecting logic. Signal delays increase as integrated circuits become denser (i.e., contain increased numbers of elements).
Computer-based simulations are often used for estimating signal delays in integrated circuits during design. In one common simulation method, a computer program solves systems of nonlinear differential equations that are derived from the state equations which describe an integrated circuit. Such simulation programs require substantial computational time and data storage and, therefore, are impractical for routine analysis of most integrated circuits of the LSI and VLSI class.
A technique called "macro-modelling" has also been used by circuit designers for simulating LSI and VLSI integrated circuits. According to this technique, macro-cells of an integrated circuit design are modelled as a small number of "standard" blocks, each of whose electrical characteristics are pre-characterized by, for example, circuit simulation. A block in a macro-modelled circuit might be, for example, a NAND gate. In this example, the pre-characterization of the block might provide a simple rule for calculating the delay at the block output as a function of the driven capacitance and of the signals arriving at input pins of the block. Using the pre-characterization rule, a system such as a logic simulator or timing verifier can predict the delay through the block.
In current practice, most logic simulators employ macro-modelling to compute delays through integrated circuits as functions of total capacitive load. These logic simulators typically perform their functions without explicitly accounting for the resistance of interconnecting paths in the simulated circuits.
Because the length of interconnecting paths in an integrated circuit normally are not known until after a physical design of the circuit has been completed, standard design practice is to use "predictive" capacitance to approximate timing delays caused by interconnecting wires in the circuit nets. (In this context, the term "nets" refers to sets of two or more circuit nodes, such as the inputs or outputs of a gate, which are joined by an interconnection.) The term "fanout one net" refers to a circuit layout net wherein a single output node of a circuit net directly drives only one other circuit net.
One problem with using conventional techniques using predictive capacitance for estimating interconnect timing delays in integrated circuits is that, after placing and routing an integrated circuit, some nets in the circuit may have capacitances substantially larger than the predicted values. In fact, the actual capacitances may exceed the predicted values even if the majority of the nets in a circuit have capacitances that are substantially smaller than their predicted values. In such cases, the majority of nets in the circuit may run faster than expected while some of the nets run much slower. Such operating speed differentials can cause timing problems which, in turn, require either manual rerouting or redesign of a circuit.
To avoid the above-discussed drawbacks, "timing-driven layout" techniques can be used. In such techniques, timing constraints are employed while placing and routing an integrated circuit. This usually involves determining timing requirements between input and output signals, and using a timing analysis tool to convert the timing requirements into layout constraints. The layout constraints can be revised as more information becomes available concerning the layout appearance. Timing-driven layout techniques are described by Michael Burnstein and Mary N. Youssef in an article entitled "Timing Influenced Layout Design" IEEE Paper 9.2, 22nd Design Automation Conference, 1982, pages 124-130.
Timing driven layout techniques cannot, however, simultaneously satisfy a large number of critical paths in an integrated circuit. Because of this limitation, circuit designers cannot specify all critical paths in large circuits without causing the timing analysis tools (which specify maximum lengths for nets) to be too slow for practical use. Consequently, timing driven layout techniques have not achieved widespread use.